Intel's new patent outlines a cross-batch memory (XBM) architecture that replaces traditional high-bandwidth memory's (HBM) silicon interposer with a design using back-end-of-line (BEOL) transistors and UCIe links. This development aims to reduce assembly costs and memory bottlenecks in AI applications, which are constrained by current memory technologies.
Intel's patent describes a new memory architecture called XBM, designed to achieve high bandwidth while reducing costs associated with traditional high-bandwidth memory (HBM). The new structure replaces the expensive silicon interposer with a stack of memory dies using back-end-of-line transistors.
The proposed memory design incorporates one-transistor one-capacitor (1T1C) DRAM implemented in BEOL, aiming for a footprint comparable to HBM4. Each memory die is approximately 1.5 GB, organized into a grid of datablocks and connected by high-bandwidth interconnects.
By eliminating the silicon interposer, Intel's XBM architecture aims to minimize assembly costs and complexity, providing a more scalable memory solution. The built-in defect repair feature enhances reliability, which is critical for demanding AI applications.
This innovation is particularly relevant as AI accelerators face limitations due to the 'memory wall'—the challenge of supplying sufficient data bandwidth. By addressing these constraints, XBM could improve performance for future AI and high-performance computing workloads.
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Intel's new patent outlines a cross-batch memory (XBM) architecture that replaces traditional high-bandwidth memory's (HBM) silicon interposer with a design using back-end-of-line (BEOL) transistors and UCIe links. This development aims to reduce assembly costs and memory bottlenecks in AI applications, which are constrained by current memory technologies.