● Covered by 1 source · 2 reportsMedium impact
Intel Reveals New Cross-Batch Memory Architecture in Patent Filing
Key points
- Intel patented Cross-Batch Memory (XBM) architecture.
- XBM replaces HBM's silicon interposer with BEOL transistors.
- UCIe links used in XBM for cost-effective design.
- XBM targets AI applications' memory bottlenecks.
- Intel's patent could influence future AI hardware.
Intel's New Memory Architecture
Intel has filed a patent for their Cross-Batch Memory (XBM) architecture, intended to overhaul traditional high-bandwidth memory (HBM) designs. Published on July 2, 2026, the patent details a shift from using costly silicon interposers to a design utilizing back-end-of-line (BEOL) transistors.
Technical Details of XBM
XBM integrates a stack of memory dies, each containing 1T1C DRAM fabricated in the back-end-of-line. These are interconnected with through-silicon via (TSV) 'gutters' and both-sided high-bandwidth interconnect (HBI) connections, intending to simplify assembly and incorporate built-in repair.
Addressing AI Memory Bottlenecks
The move to replace HBM's existing architecture aims to address the bottlenecks in memory bandwidth and cost that are significant in AI applications. By eliminating the silicon interposer, Intel proposes to reduce expenses associated with conventional HBM technologies, thereby potentially enhancing AI capabilities.
Potential Impact on AI Hardware
This development suggests that Intel is actively working to innovate within the AI hardware space. With the potential to reduce costs and improve the performance of AI accelerators, this patent filing could influence future designs and implementations in the industry.
✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →
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How outlets covered it
Researchers have proposed two novel memory designs, V-Die and MOSAIC, to improve HBM performance and reduce heat issues in AI accelerators. These designs permit higher bandwidth and density, addressing the bottleneck of data movement critical for advanced AI tasks.
Intel's new patent outlines a cross-batch memory (XBM) architecture that replaces traditional high-bandwidth memory's (HBM) silicon interposer with a design using back-end-of-line (BEOL) transistors and UCIe links. This development aims to reduce assembly costs and memory bottlenecks in AI applications, which are constrained by current memory technologies.