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ESBMC-Arduino Enhances Formal Verification for Open-Hardware PLCs

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Key points

  • Introduces a hardware abstraction layer for IEC 61131-3 verification.
  • Reduces false alarms from 44% to zero in tested programs.
  • Targets low-cost microcontrollers for industrial control systems.

Introduction to ESBMC-Arduino

ESBMC-Arduino aims to enhance formal verification for open-source programmable logic controllers (PLCs) such as Arduino-based systems. The project is particularly relevant for low-cost microcontrollers used in industrial automation, providing a sound framework for ensuring system safety in environments constrained by hardware capacities.

Limitations of Current Verification Techniques

Existing tools like ESBMC-PLC use abstract models for verification, leading to inaccurate results when applied to resource-constrained hardware. The naive width-aware verification process resulted in a high false alarm rate, where 44% of checks flagged non-existent issues due to unrealistic input models.

Innovative Hardware Abstraction Layer

ESBMC-Arduino introduces a declarative hardware abstraction layer (HAL) to alleviate these verification challenges. By accurately simulating the fixed-width arithmetic and incorporating real sensor readings through an analog-to-digital converter, the tool creates a more realistic model for testing automation software.

Validation Results

Testing on a corpus of 123 real programs demonstrated that the new HAL annotator eliminated all 54 previously identified false alarms. This improvement allows users to maintain robust safety proofs while effectively identifying true width-dependent defects.

Significance for the Tech Industry

The development of ESBMC-Arduino represents an important advancement in formal verification, particularly in the domain of open-hardware PLCs. By providing reliable methods for error-checking in low-cost industrial controls, it enhances the safety and reliability of modern automation systems.

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Primary sources

arXiv 2607.08550

Reporting from

ESBMC-Arduino addresses the limitations of existing open-source verifiers for IEC 61131-3 on microcontrollers. By introducing a hardware abstraction layer that models finite-width arithmetic, it reduces false alarm rates while verifying safety in automation programs.