Intel's x86 Ecosystem Advisory Group has unveiled the ACE framework, a new accelerator type designed to optimize matrix multiplication in machine learning workloads. ACE builds upon the existing AMX extension, simplifying tile register configurations while introducing outer product instructions and supporting FP8 data types.
The x86 Ecosystem Advisory Group has published a new specification for the ACE framework, which serves as a new accelerator type alongside Intel’s existing Advanced Matrix Extensions (AMX). This initiative aims to enhance CPU performance for machine learning by optimizing matrix multiplication operations.
While AMX allows for extensive configuration of matrix tile parameters, ACE simplifies this by defining tile registers consistently as 64 bytes by 16 rows. Moreover, unlike AMX, ACE excludes support for complex numbers, focusing instead on new FP8 data types.
The ACE framework can be compared to Arm's Scalable Matrix Extension (SME) and its subsequent SME2 expansion. Both frameworks aim to achieve low-latency matrix multiplication, but differ in their architectural implementations. ACE retains AMX's 8 KB of tile registers while Arm's SME offers a variable streaming vector length for greater flexibility.
The introduction of the ACE framework reflects Intel’s commitment to evolving its CPU architectures in response to growing machine learning workloads. As CPUs integrate more sophisticated instruction sets, the industry anticipates greater performance efficiencies when executing relevant applications.
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Intel's x86 Ecosystem Advisory Group has unveiled the ACE framework, a new accelerator type designed to optimize matrix multiplication in machine learning workloads. ACE builds upon the existing AMX extension, simplifying tile register configurations while introducing outer product instructions and supporting FP8 data types.