AMD has provided initial details for its Zen 6 Epyc "Venice" server processors, which have been teased for over a year. The company plans a "broad portfolio" for Venice, including purpose-built solutions for different applications. This strategy is similar to how Intel has segmented its Xeon ranges and AMD has previously segmented its Epyc offerings.
The Venice-X CPU is scheduled for release in the second half of 2027. It will feature 96 cores, 1152 MB of 3D V-Cache, and clock speeds up to 5.15 GHz. This processor is built on the Zen 6 microarchitecture, the same as Venice SP7, and is designed for high-performance computing (HPC) workloads. Venice-X supports 16-channel memory with standard DDR5 RDIMMs.
The Epyc 9996 is a 256-core / 512-thread chip, representing the first Zen 6 CPU in the Venice lineup. This variant utilizes AMD's Zen 6c "dense" design to achieve its 256-core count. It offers up to 1.6 TB/s of memory bandwidth with fast MRDIMMs and 128 PCIe 6 lanes in a 1P configuration, or 160 lanes in a 2P configuration.
AMD claims significant performance advantages for its Zen 6 Epyc processors. The company states that the Epyc 9996 can achieve up to a 3.4x performance increase over Intel Xeon competition and a 20% increase over Nvidia Vera in certain configurations. The Venice-X also features higher clock speeds compared to previous Epyc variants like the 96-core Epyc 9684X, which clocks up to 3.7 GHz.
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AMD has released initial details for its Zen 6 Epyc "Venice" server processors, including a 256-core variant and a roadmap for future models. These new processors are designed to compete with Intel Xeon and Nvidia Vera offerings, with AMD claiming significant performance advantages in certain configurations.
AMD announced its Venice-X CPU, scheduled for release in the second half of 2027, featuring 1152 MB of 3D V-Cache, 96 cores, and a 5.15 GHz boost clock. This Zen 6 microarchitecture-based processor targets high-performance computing (HPC) workloads with its large cache and high clock speeds.