Esp32sim Enables In-Browser Emulation of ESP32 Firmware Across Four SoCs

In-Browser ESP32 Emulation

Esp32sim offers instruction-level emulation for four different ESP32 System-on-Chips (SoCs) directly within a web browser. This includes support for both of Espressif's CPU architectures. The emulation boots the actual mask ROM, the second-stage bootloader, and unmodified application images, allowing for end-to-end execution of real projects without requiring patched firmware or stubs.

Supported SoCs and Peripherals

The emulation covers the classic ESP32, ESP32-C3, ESP32-C6, and ESP32-S3. It models essential SoC components such as GPIO, UART, and timers. For example, the classic ESP32 emulation includes dual LX6 cores and basic peripherals. The C3 and C6 reuse many peripheral models from the S3, including UART, USB-Serial/JTAG, systimer, timer groups, GPIO, SPI flash controller, GDMA, and SHA/AES/RSA, while adding their own memory maps and cache controllers.

Architecture and Components

The Esp32sim project is structured into several core components. The `emu-core` handles Bus and Core traits, Trap, and ClockTree, shared across both CPU architectures. The `esp-soc` component manages the scheduler, device time, console, and web UI, acting as the machine for each chip. `esp-periph` contains models for shared peripheral IP like UART, systimer, TIMG, GPIO, SPI_MEM, GDMA, and crypto. CPU-specific crates, such as `xtensa-lx7` for the ESP32-S3, provide decoders, interpreters, and JIT compilers.

Accessibility and Use Cases

The emulator is accessible via a web browser, requiring no installation or accounts. This setup allows developers to test and debug ESP32 firmware in a virtual environment. Demos available include Linux on the S3, a Touch-LCD-4B panel with a SID player, an LLM aquarium, and specific demonstrations for the C3 and C6 chips.