Dave Plummer, known for his work on Microsoft products like Task Manager, undertook a project to create a custom RAM board for his 1970s PDP-11 computer. The motivation stemmed from the high cost of acquiring original memory for the vintage machine, which could support up to four megabytes of RAM in later models.
Plummer leveraged modern tools, including ChatGPT for assistance and the EasyEDA online circuit simulator, to design the new RAM board. The design was made as a standalone Q-Bus compatible card, intended to operate alongside the system's M8190 CPU. Key components included a Lattice MachXO2 FPGA (model 2000HC) acting as the memory controller, connected to four ISSI 1MB memory chips. The circuit also incorporated a U2S I/O chip, DIP switches, and communication ports.
The project faced initial hurdles, including Plummer's inexperience with flash-programming FPGA chips. After resolving this, a more significant issue arose concerning the PDP-11's memory bus architecture. The PDP-11 accesses memory in two-byte words and uses the lowest bit of an address as a byte selector within that word. This meant the memory controller needed to return two bytes on reads and selectively update bytes on writes, despite the bus carrying full words.
Plummer initially missed this detail, leading to the memory only returning every second word. This issue was identified by commenters, suggesting a fix would involve adjusting the FPGA's memory controller code to correctly handle the PDP-11's word-addressing scheme.
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Dave Plummer, a former Microsoft engineer, designed and built a custom 4MB RAM board for his vintage PDP-11 computer. He utilized ChatGPT and EasyEDA for the design process, creating a Q-Bus compatible card with an FPGA controller and ISSI memory chips. The project encountered a challenge with the PDP-11's word-addressable memory bus, which required an adjustment to the FPGA's memory controller logic.