● Covered by 1 source · 1 reportMedium impact1 neutral
Nagare Labs develops Z2RAM, a memory technology combining SRAM speed with DRAM density
Key points
- Z2RAM offers SRAM speed at DRAM density for AI chips.
- Gen 1 projects 5x SRAM density, 14x DRAM speed, 3x less read energy.
- Uses a two-transistor, no-capacitor cell design.
- 3D stacks layers directly on accelerator without interposers or bonding.
Introducing Z2RAM Memory Technology
Nagare Labs, a Georgia Tech spinout backed by Pat Gelsinger, has announced Z2RAM, a new memory technology. Z2RAM is designed to integrate SRAM-speed memory with DRAM density directly onto AI chips. This development aims to overcome current memory bandwidth and density challenges in high-performance computing.
Performance and Efficiency Targets
The first generation of Z2RAM is projected to achieve five times the density of SRAM, 14 times the speed of DRAM, and consume three times less read energy than SRAM. Early tests of the memory cell, conducted up to 85 degrees Celsius, demonstrated data retention for over 300 seconds. The company aims for energy consumption well under a picojoule per bit.
Addressing AI Chip Memory Bottlenecks
AI chips require significant memory bandwidth, which current High-Bandwidth Memory (HBM) solutions struggle to provide efficiently due to yield issues and heat dissipation. Alternatives like high-bandwidth flash and stacked SRAM have their own limitations regarding density, cost, or speed. Z2RAM seeks to provide a solution that combines the advantages of speed and density without the thermal and manufacturing complexities of existing stacked memory technologies.
The memory bandwidth growth (20% per year) has lagged behind peak compute growth (70% per year) over the past three decades, creating a bottleneck that Z2RAM intends to alleviate.
Innovative Design and Manufacturing
Z2RAM's design features "Two transistors and a shield" and no capacitor. A write transistor places a charge on a storage node, and a shield blocks interference. The read transistor senses without draining the charge, making reads non-destructive and eliminating the need for DRAM's write-back cycle. The cell's gain-cell structure uses the read transistor's gate capacitance to hold the charge.
Nagare Labs manufactures Z2RAM by depositing and patterning layers directly on top of the accelerator, similar to 3D NAND flash scaling. This process eliminates the need for interposers and bonding between memory layers. The technology uses standard 300 mm tools with DUV lithography, avoiding the need for EUV, and has a roadmap targeting over 100 layers.
✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →
The daily brief
One email each morning: the day's tech stories, clustered across outlets and summarized. No account needed.
One email a day. Unsubscribe in one click, any time.
Today's brief
Spend a few minutes, get the whole day. Every topic's top stories in one hands-free rundown — listen, watch, or read the transcript.
▶ Play today's brief
New every morning, and the back catalogue is archived by date.
Reporting from
Nagare Labs, a Georgia Tech spinout, introduced Z2RAM, a new memory technology that aims to provide SRAM-level speed at DRAM density, directly on AI chips. This technology addresses the memory bandwidth limitations of AI chips by offering higher density and speed with lower power consumption compared to existing solutions like HBM and SRAM. Z2RAM uses a novel two-transistor, no-capacitor cell design and a 3D stacking process that avoids interposers and bonding.