In May 2026, NASA announced its High Performance Spaceflight Computing (HPSC) processor and began a testing phase at the Jet Propulsion Laboratory (JPL). This development marks a shift from traditional spacecraft processors that prioritized survivability over performance due to the harsh space environment.
Built in partnership with Microchip Technology, the HPSC processor, specifically the Microchip PIC64-HPSC, integrates multi-core computing, high-speed networking, fault tolerance, AI readiness, and security. It is a 64-bit multi-core system-on-chip (SoC) architecture engineered with radiation-hardened-by-design principles for spaceflight applications.
NASA expects HPSC to deliver a hundredfold improvement in performance per watt over existing space-qualified computing systems. This power efficiency allows more resources to be allocated to instruments, communications, or mobility systems on missions ranging from Earth orbit to deep space.
Current space exploration demands require more onboard autonomy, sophisticated science instruments, and faster decision-making, which traditional processors struggle to support. HPSC was created to address these challenges by providing increased computing capacity while maintaining resilience against radiation and extreme temperatures. This enables new methods for solar system exploration.
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NASA's High Performance Spaceflight Computing (HPSC) processor, developed with Microchip Technology, has entered a testing phase at JPL. This new radiation-hardened system is designed to deliver a hundredfold improvement in performance per watt compared to current space-qualified systems, enabling more advanced space exploration missions.