New ASIC Reverse Engineering Puzzle Released

ASIC Reverse Engineering Challenge

A new puzzle has been released that focuses on reverse engineering an Application-Specific Integrated Circuit (ASIC). Participants are given the final mask of a custom-designed ASIC, which includes all its metal, routing, and active transistor layers, along with sample inputs and outputs.

Puzzle Objectives

The primary goal of the puzzle is to recover the netlist from the provided layout. Following this, participants must determine the true purpose and functionality of the circuit. The final step involves using the understood chip functionality to deduce a specific output and find a hidden string value.

Chip Design Process Overview

Modern chip creation begins with hardware description languages like Verilog, which are synthesized into a netlist of logic gates. Electronic design automation tools then place and route these gates, connecting them with metal wires across multiple layers. The output is a GDS file, a geometric description used by foundries to fabricate the silicon. This GDS file contains all the information about the chip's functionality, though it is unlabeled.

Guidance for Participants

Participants are advised to examine the physical arrangement of the circuit for hints regarding its functionality. An isolated section of the design, used for output generation but not affecting the output, can be ignored during initial reverse-engineering. A method to simulate the underlying circuit is necessary to test solutions and obtain the final output. The correct solution is indicated when a specific output signal goes high after toggling the reset signal for each input attempt.