Intel's forthcoming Nova Lake CPUs are now rumored to feature larger L3 cache pools for certain configurations with disabled E-core clusters. Previously, it was anticipated that SKUs with fewer active E-cores would also have a proportionally reduced L3 cache. However, new information from tipster Jaykihn indicates that Intel may keep the L3 cache unaltered for some of these chips.
The 8+12+4 Nova Lake configuration, which was expected to have 33MB of L3 cache due to its 12 E-cores being a cut-down version of a 16 E-core variant, is now predicted to have 36MB of L3 cache. Similarly, the 4+4+4 configuration is now expected to feature 18MB of L3 cache, up from the previously rumored 15MB. These revised figures match the L3 cache amounts of their fully enabled counterparts (8+16+4 and 4+8+4, respectively).
This cache retention strategy does not apply uniformly across all Nova Lake SKUs. For example, the 6+12+4 configuration is still expected to be limited to 27MB of L3 cache, rather than the 30MB it would have if its disabled E-core cluster retained its full cache. This suggests that Intel is selectively deciding which SKUs benefit from full L3 cache retention, rather than implementing a linear scaling approach.
The reported changes are not limited to Nova Lake desktop CPUs; the Nova Lake-HX mobile lineup is also expected to follow the same methodology. This could result in some midrange mobile SKUs having more L3 cache than initially anticipated. All information remains preliminary and subject to change before the official launch, potentially at CES 2027.
Nova Lake is also expected to introduce bLLC (Big Last Level Cache) in consumer CPUs, intended to compete with AMD's 3D V-Cache. Mid- to high-end SKUs, including the 8+12+4 and 6+12+4 configurations, are rumored to feature 132MB and 108MB of bLLC, respectively. This bLLC is distinct from the native L3 cache discussed in these leaks, and its predicted sizes are not affected by the current L3 cache revisions.
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New leaks suggest Intel's upcoming Nova Lake CPUs with partially disabled E-core clusters will retain their full L3 cache pool, contrary to earlier rumors. This change means certain configurations, like the 8+12+4 and 4+4+4, are now predicted to have larger L3 cache amounts than previously expected, potentially affecting performance for some midrange SKUs.