Project Oberon System Migrated to RISC-V Architecture

Project Oberon System Update

The Project Oberon System has been updated, transitioning from the Oberon 07 language version to the more widely used Oberon 90. This migration incorporates a recent version of the OP2 compiler, which now features a RISC-V (RV32) backend, enabling the system to run on this open-source hardware architecture.

Emulation and Compatibility

The updated repository includes an emulation of the original Project Oberon machine, as described by Wirth in his book. This emulator is based on a stripped-down RV32 emulator, combined with a custom implementation of the machine and its peripherals. The memory map of Wirth's original machine is precisely reproduced, ensuring that core modules like Kernel.Mod, Display.Mod, and Input.Mod remain unchanged and functional.

Background of Project Oberon

Project Oberon was initially conceived and implemented between 1986 and 1989 by Niklaus Wirth and Jürg Gutknecht at ETH Zürich. It encompassed an entire computer system, including an operating system, compiler, programming language, and editors. The project was documented in the 1992 book "Project Oberon - The Design of an Operating System and Compiler."

Wirth continued to develop the project, releasing sources in Oberon-07, a simplified version of the language. A 2013 revision of the Project Oberon book is also available, maintaining the original goal of providing a comprehensive example of a functional system.

Hardware Evolution

The 1992 Project Oberon utilized the National Semiconductor NS32032 processor. Due to the obsolescence of this processor, Wirth designed his own processor, named RISC-5, to maintain simplicity and regularity in the hardware. This custom processor was implemented on an FPGA, allowing the entire Oberon System to run on a low-cost development board like the Xilinx Spartan-3. The hardware modules are described in Verilog and are available on projectoberon.net.