● Covered by 2 sources · 2 reportsMedium impact2 neutral
Qwenputer embeds a functioning, deterministic RISC-V CPU within Qwen 3.5's weights
Key points
- Qwenputer is a Qwen 3.5 4B model with an embedded RISC-V CPU.
- The CPU uses the model's Gated DeltaNet attention layers as RAM.
- It runs arithmetic, C, and MicroPython code internally.
- No external runtime, tools, or plugins are required.
- The model is available on Hugging Face and ModelScope.
- Divyansh Agrawal developed Qwenputer.
- The CPU is 32-bit.
- Qwenputer can run Doom.
- The CPU implementation uses 11 transformer layers.
- The CPU weights are computed by a compiler, not learned.
- Qwenputer's CPU passes official riscv-tests.
Qwenputer: An Embedded RISC-V CPU
Qwenputer is an experimental model based on Qwen 3.5 4B that incorporates a RISC-V CPU directly within its weights. This CPU operates entirely within the model's forward passes, enabling it to perform arithmetic operations and execute C and MicroPython code. The implementation does not rely on external plugins, tools, or sandboxes.
Gated DeltaNet as RAM
The core innovation involves using Qwen 3.5's Gated DeltaNet (GDN) attention layers as the CPU's RAM. Qwen3-Next and Qwen 3.5 utilize GDN, a linear RNN, for three out of four attention layers. Each GDN head maintains a state matrix, which functions as memory.
By configuring the gate to 1, the write strength (beta) to 1, and employing one-hot key encoding, each write operation overwrites a specific row in the state matrix. Similarly, one-hot queries can retrieve exact values. This setup allows the GDN layers to function as exact RAM, offering a lower-cost alternative to using standard attention mechanisms for memory.
Internal File Storage and Future Implications
Beyond the CPU and RAM integration, Qwenputer also includes experimental in-model file storage. This development opens avenues for hybrid models to conceal reasoning within their RNN states, potentially evading Chain-of-Thought (CoT) monitoring. Additionally, compiled weights like those in Qwenputer could serve as tamper-proof internal monitoring tools within models.
Availability
The Qwenputer model is accessible on Hugging Face and ModelScope. The associated code is available on GitHub for further exploration and development.
Updates
- Divyansh Agrawal developed Qwenputer.
- The CPU is 32-bit.
- Qwenputer can run Doom.
- The CPU implementation uses 11 transformer layers.
- The CPU weights are computed by a compiler, not learned.
- Qwenputer's CPU passes official riscv-tests.
✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →
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How outlets covered it
AI engineer Divyansh Agrawal developed Qwenputer, an experimental Qwen 3.5 4B LLM with a 32-bit RISC-V CPU compiled directly into its weights, allowing it to perform arithmetic operations and run C/MicroPython code internally. This integration enables the LLM to execute programs like Doom without external runtimes and includes a persistent filesystem, addressing LLM arithmetic limitations and expanding functional capabilities.
A new experimental model, Qwenputer, integrates a RISC-V CPU directly into the weights of a stock Qwen 3.5 4B model, utilizing its Gated DeltaNet attention layers as RAM. This allows the model to execute arithmetic operations, C, and MicroPython code internally without external tools or runtimes, demonstrating a novel method for embedding computational capabilities within large language models.