Research Bridges Gap Between Experimental and Device-Level Modeling of DRAM Read Disturbance

Addressing DRAM Read Disturbance Inconsistencies

DRAM read disturbance, including RowHammer and RowPress, is a known issue where accessing one DRAM location can cause unintended bitflips in other unaccessed locations. This phenomenon impacts the reliability and security of DRAM-based computing systems. While experimental studies have characterized these bitflips and proposed mitigations, existing device-level models of the underlying physical mechanisms do not fully explain all empirical observations.

Bridging Experimental and Device-Level Understanding

The research aims to reconcile the differences between experimental characterization and device-level modeling of RowHammer and RowPress. It identifies gaps and inconsistencies in how existing device-level models explain bitflip directions, bitflip counts, and the minimum number of aggressor row activations (ACmin) required to trigger bitflips. These metrics are fundamental to understanding the physical mechanisms involved.

TCAD Simulations Validate Phenomena

To bridge this gap, the study presents a comprehensive set of TCAD simulations. These simulations were designed to match phenomena observed in experimental characterizations of RowHammer and RowPress bitflips. The results from these simulations provide a more aligned understanding of the disturbance mechanisms.

Updated Error Mechanisms and Modeling Parameters

The research summarizes updated device-level error mechanisms for understanding RowHammer and RowPress bitflips based on the simulation results. It also identifies key modeling and simulation parameters that significantly influence whether simulation outcomes align with real-chip characterization data. This work provides a foundation for future research in understanding, characterizing, and mitigating DRAM read disturbance.

Implications for Mitigation and Characterization

The findings have implications for developing more rigorous, comprehensive, and efficient experimental characterization methodologies for DRAM read disturbance bitflips. Additionally, the insights gained can inform the design of more effective mitigation techniques against these types of memory vulnerabilities. This research contributes to a more principled approach to addressing DRAM reliability and security concerns.