● Covered by 2 sources · 2 reportsLow impact2 neutral
Researcher Identifies x86 Instruction Taking 62 Seconds to Execute
Key points
- Christopher Domas created the "CPU Deoptimization" project.
- The project identifies the slowest single x86 instruction.
- `fxrstor64` took 62 seconds (198 billion cycles) to execute.
- Execution occurred on an AMD Ryzen 7 5800H processor.
- High-latency MMIO regions and PCIe fabric saturation were used.
The Slowest Instruction
Hardware researcher Christopher Domas initiated the "CPU Deoptimization" project, also referred to as the "Assembly Hall of Shame," with the goal of identifying the single x86 instruction that takes the longest to execute. This project contrasts with typical instruction latency analysis, which focuses on optimizing performance.
The current record holder for the slowest instruction is `fxrstor64`. On an AMD Ryzen 7 5800H processor, this instruction completed in 62 seconds, equivalent to 198,002,498,236 cycles.
Methodology for Maximizing Latency
To achieve this extreme latency, Domas employed a specific strategy. The `fxrstor64` instruction was used to load a 512-byte FPU/MMX/XMM state from a high-latency Memory-Mapped I/O (MMIO) region within the PCIe fabric. This initial step alone resulted in 74 billion cycles, or over 23 seconds.
Further increasing the execution time involved "starving the fabric while the load is in flight." This was accomplished by using multiple "hammer cores" to continuously access a different high-latency MMIO register with tight 4-byte reads. This action saturated the PCIe root complex and endpoint with non-posted transactions, forcing the 512-byte `fxrstor64` load to queue behind the contending traffic, thereby maximizing its latency.
Beyond `fxrstor64`
The project also noted other examples of extreme latency, such as a spec-violating unaligned `ymm0` load. This specific load forced non-posted dword transactions from stalled GPU registers, which was used to disrupt the fundamental design of System Management Mode in a separate instance.
Implications for Processor Architecture
This research provides insights into potential performance bottlenecks and architectural limitations within processors. By exploring the inverse of performance optimization, the project highlights how specific instruction and system configurations can lead to exceptionally long execution times, offering a unique perspective on processor behavior.
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Primary sources
GitHub cmc_internal/api GitHub github/collect GitHub xoreaxeaxeax/asm-hall-of-shame GitHub _private/browser GitHub get-started/accessibility GitHub open-source/sponsorsHow outlets covered it
Hardware researcher Christopher Domas created a "CPU Deoptimization" project to find the slowest single x86 instruction, identifying fxrstor64 as the current slowest, taking 62 seconds or 198 billion cycles. This research explores the inverse of performance optimization by intentionally maximizing instruction latency, providing insights into processor architecture and potential bottlenecks.
The "Assembly Hall of Shame" project investigates the slowest possible execution times for single CPU instructions, contrasting with typical performance optimization efforts. This research identifies specific instruction and system configurations that maximize latency, offering insights into potential performance bottlenecks and architectural limitations.