SK hynix to integrate custom H-TPU cores into SSD controllers to offload Arm CPUs

Introduction of H-TPU Cores

SK hynix announced plans to integrate custom Hynix Transaction Processing Unit (H-TPU) cores into its SSD controllers. These cores are designed to manage repetitive I/O operations, aiming to decrease the reliance on power-intensive general-purpose CPU cores.

The H-TPU is distinct from AI accelerators and features a four-stage, in-order pipeline. It is intended to handle routine tasks, allowing the traditional Arm CPU to focus on management functions.

Addressing Scaling Challenges in SSDs

Koo In-jae, SK hynix's VP of system-on-chip (SoC) design, stated at ISOCC 2026 that SSD controller CPUs are reaching their limits in terms of power consumption and physical area. With PCIe bandwidth doubling each generation, controller CPU clocks and control capabilities struggle to keep pace.

The company intends to deploy H-TPU technology across its NAND product range, including next-generation enterprise SSD controllers, where the demand for IOPS is particularly high.

Efficiency and Design of H-TPU

The H-TPU cores are designed to be small and programmable, consuming approximately 2.5% of the power and occupying about 4% of the area of a general-purpose CPU core. SK hynix provides a dedicated compiler and development tools for these specialized cores.

These cores are not superscalar and do not use out-of-order execution. Their primary functions include processing read and write commands, managing metadata, and controlling buffers.

Functional Distribution

Storage control involves over 100 detailed functions. Instead of relying on a monolithic CPU, SK hynix has distributed these functions across multiple small H-TPU clusters. This approach aims to optimize performance and efficiency by assigning specific, repetitive tasks to the specialized H-TPU cores.