Rapidus to Offer Lower Wafer Prices than TSMC for 2nm Class Silicon

Pricing Strategy and Timing

Atsuyoshi Koike, the CEO of Rapidus, detailed the company's strategy to undercut TSMC on wafer pricing by offering a competitive rate of ¥3 million to ¥3.5 million ($18,550 - $21,635) per processed wafer. This pricing is considerably lower than TSMC's rumored costs of around $30,000 per wafer for its N2 process. Rapidus plans to initiate high-volume manufacturing (HVM) in the second half of 2027.

Competitive Landscape

In the context of the semiconductor market, Rapidus is set to compete not only against TSMC but also against Samsung's anticipated SF2 offerings at roughly $20,000 per wafer. However, significant production volumes from Rapidus are expected to ramp up only in 2028, coinciding with TSMC's rollout of its N2P node.

Challenges Ahead for Rapidus

Despite its attractive pricing, Rapidus faces substantial challenges in competing with TSMC's advanced manufacturing capabilities and established ecosystem. TSMC's Open Innovation Platform (OIP) includes advanced electronic design automation tools and comprehensive support from various partners, which Rapidus, alongside competitors like Intel and Samsung, currently lacks.

Conclusion

While Rapidus's lower pricing could lure some customers, the longstanding technological and process prowess of TSMC may mitigate the effectiveness of this strategy. The success of Rapidus’s approach will largely depend on its ability to scale operations efficiently and overcome the technological gaps as it enters the highly competitive semiconductor market.