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SK hynix Delays Hybrid Bonding for HBM to HBM5, Citing 775-Micron Thickness Limit
Key points
- Hybrid bonding for HBM is delayed until HBM5.
- HBM cubes are limited to 775 microns in thickness.
- 16-Hi HBM4 uses 50-micron dies and halved gaps.
- SK hynix continues to use MR-MUF for HBM4.
- HBM requires three times the wafer area of DDR5 for the same capacity.
- Micron HBM Design Architecture Fellow Raghu Sreeramaneni spoke at Hot Chips 2026.
- Conventional DRAM contract prices rose 90-95% in Q1 2026 and 58-63% in Q2 2026.
- An HBM4 die has 256 banks, while a DDR5 die has 32 banks.
- A single HBM3E die feeds 256 GB/s.
- OXMIQ Labs presented at Hot Chips 2026.
- High Bandwidth Flash (HBF) cannot replace HBM for most workloads.
- HBF can serve as a specialized memory tier for large, less frequently accessed datasets.
- SanDisk unveiled the High-Bandwidth Flash (HBF) concept in early 2025.
- HBF Grade 1 uses an 8-Hi 256GB NAND stack with an 8 GT/s UCIe interface and 384 GB/s bandwidth.
- HBF Grade 2 uses a 512GB NAND stack with a 16 GT/s UCIe interface and 1.536 TB/s bandwidth.
- HBF Grade 3 reaches 3.072 TB/s using 32 GT/s UCIe 2.0 with 512 GB capacity.
- HBF supports read block sizes between 64 bytes and 4 kilobytes, 4KB writes, and 4KB page sizes.
- Samsung unveiled a three-phase HBM roadmap at Hot Chips 2026.
- Samsung's zHBM architecture places DRAM directly on the processor.
- Samsung's Sangwook Han of the DRAM design team detailed the roadmap.
- Samsung moved the HBM base die to a 4nm logic process starting with HBM4.
- Samsung announced its HBM5 goal at the Memory Executive Summit preceding Semicon Taiwan 2026.
- HBM5 aims to improve performance per watt by 20% compared to HBM4E.
- Samsung's Choi Jang-seok, head of product planning, detailed HBM5 goals.
- Samsung HBM5 memory stacks will feature a heat path block (HPB).
- HPB will reduce thermal resistance by 20% and simplify HBM5 cooling.
- HBM5 could achieve 4 TB/s per stack by 2028-2029.
- TSMC expects AI accelerators to use 20-24 HBM5/HBM5E per package by 2030.
- TSMC has scaled its SoIC bond pitch from 9 microns to 6 microns.
- TSMC plans to reach 4.5 micron bond pitch by 2029.
- Intel began shipping Foveros Direct hybrid bonding in Clearwater Forest server CPU in H1 2026.
- AMD has used hybrid bonding in volume since the first 3D V-Cache parts.
- JEDEC raised the HBM stack-height limit, allowing HBM4 to use microbump technology.
- Hybrid bonding for HBM is now set to debut in HBM4E and HBM5.
Hybrid Bonding Delayed for HBM
SK hynix Vice President of Package Engineering, Jaesik Lee, stated at Hot Chips 2026 that hybrid bonding will not be implemented for HBM4E. The company now anticipates its adoption for HBM5 at the earliest. This pushes back a significant memory packaging transition that was previously expected sooner by some in the industry.
The 775-Micron Thickness Constraint
The primary reason for the delay is the 775-micron total thickness limit for HBM cubes, which matches the standard thickness of a 300mm logic wafer. This limit is critical because when a GPU package's cold plate is attached, both the logic die and memory stacks are ground to expose bare silicon. A memory cube exceeding 775 microns would protrude above the processor, creating integration issues.
To accommodate more DRAM layers within this constraint, each additional layer requires thinner dies and narrower gaps. For example, 16-Hi HBM4, currently in customer qualification, uses core dies around 50 microns thick and halves the gap between them compared to 12-Hi configurations.
Manufacturing Challenges and Thermal Burden
Thinner dies lead to a proportionally higher oxide content in the stack, which conducts heat less efficiently than silicon. Concurrently, pin speeds have increased from 1 Gbps in early HBM to 8 Gbps in HBM4, concentrating more power within the same footprint. SK hynix data indicates a 2.2 times higher thermal burden across HBM generations, with stack counts doubling every two generations.
SK hynix's current mass reflow-molded underfill (MR-MUF) process, which stacks dies via pick-and-place and joins them in a single reflow, faces challenges with these shrinking gaps and sub-50-micron dies. Controlling warpage in such conditions is a major manufacturing hurdle for 16-Hi HBM.
Industry Context
Samsung had previously committed to hybrid bonding for HBM4 in May of the prior year. SK hynix, however, considered the copper-to-copper technique as a backup to its advanced MR-MUF process. The JEDEC HBM4 standard's increase of the package thickness ceiling from 720 microns to 775 microns reduced the immediate pressure to adopt hybrid bonding, contributing to its delayed implementation.
Updates
- Samsung announced its HBM5 goal at the Memory Executive Summit preceding Semicon Taiwan 2026.
- HBM5 aims to improve performance per watt by 20% compared to HBM4E.
- Samsung's Choi Jang-seok, head of product planning, detailed HBM5 goals.
- Samsung HBM5 memory stacks will feature a heat path block (HPB).
- HPB will reduce thermal resistance by 20% and simplify HBM5 cooling.
- HBM5 could achieve 4 TB/s per stack by 2028-2029.
- TSMC expects AI accelerators to use 20-24 HBM5/HBM5E per package by 2030.
- TSMC has scaled its SoIC bond pitch from 9 microns to 6 microns.
- TSMC plans to reach 4.5 micron bond pitch by 2029.
- Intel began shipping Foveros Direct hybrid bonding in Clearwater Forest server CPU in H1 2026.
- AMD has used hybrid bonding in volume since the first 3D V-Cache parts.
- JEDEC raised the HBM stack-height limit, allowing HBM4 to use microbump technology.
- Hybrid bonding for HBM is now set to debut in HBM4E and HBM5.
- Samsung unveiled a three-phase HBM roadmap at Hot Chips 2026.
- Samsung's zHBM architecture places DRAM directly on the processor.
- Samsung's Sangwook Han of the DRAM design team detailed the roadmap.
- Samsung moved the HBM base die to a 4nm logic process starting with HBM4.
- OXMIQ Labs presented at Hot Chips 2026.
- High Bandwidth Flash (HBF) cannot replace HBM for most workloads.
- HBF can serve as a specialized memory tier for large, less frequently accessed datasets.
- SanDisk unveiled the High-Bandwidth Flash (HBF) concept in early 2025.
- HBF Grade 1 uses an 8-Hi 256GB NAND stack with an 8 GT/s UCIe interface and 384 GB/s bandwidth.
- HBF Grade 2 uses a 512GB NAND stack with a 16 GT/s UCIe interface and 1.536 TB/s bandwidth.
- HBF Grade 3 reaches 3.072 TB/s using 32 GT/s UCIe 2.0 with 512 GB capacity.
- HBF supports read block sizes between 64 bytes and 4 kilobytes, 4KB writes, and 4KB page sizes.
- HBM requires three times the wafer area of DDR5 for the same capacity.
- Micron HBM Design Architecture Fellow Raghu Sreeramaneni spoke at Hot Chips 2026.
- Conventional DRAM contract prices rose 90-95% in Q1 2026 and 58-63% in Q2 2026.
- An HBM4 die has 256 banks, while a DDR5 die has 32 banks.
- A single HBM3E die feeds 256 GB/s.
✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →
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How outlets covered it
Hybrid bonding, a copper-to-copper joining technique for 3D chip stacks, is in high-volume production for logic chips with TSMC scaling to 6 microns and Intel shipping Foveros Direct. However, its adoption in High-Bandwidth Memory (HBM) has been postponed due to a JEDEC decision allowing HBM4 to continue using microbump technology, pushing hybrid bonding's HBM debut to HBM4E and HBM5 at the end of the decade.
Samsung announced its goal for the next-generation HBM5 memory specification to double performance and increase power efficiency compared to HBM4E. This performance increase may involve doubling the interface width to 4,096 bits, as doubling the per-pin data transfer rate is more challenging.
Samsung detailed a three-phase roadmap at Hot Chips 2026 to evolve High-Bandwidth Memory (HBM) into an integrated memory-and-compute system, culminating in zHBM, which places DRAM directly on the processor. This development aims to overcome bandwidth and power limitations in current HBM architectures by progressively offloading functions into a more capable base die.
OXMIQ Labs presented at Hot Chips 2026 that High Bandwidth Flash (HBF) cannot replace High Bandwidth Memory (HBM) for most workloads, but can serve as a specialized memory tier for large, less frequently accessed datasets. This analysis clarifies the role of HBF, which was initially presented as a potential HBM alternative, by detailing its performance and capacity trade-offs.
Micron reported at Hot Chips 2026 that High Bandwidth Memory (HBM) requires roughly three times the wafer area of DDR5 for the same capacity, a penalty that is increasing with each generation. This growing silicon demand for HBM, particularly for AI applications, is a factor in the significant rise in conventional DRAM contract prices, which increased 90-95% in Q1 2026 and 58-63% in Q2 2026.
SK hynix announced that hybrid bonding technology for High Bandwidth Memory (HBM) will not be ready for HBM4E and is now projected for HBM5 at the earliest. This delay is due to the industry-standard 775-micron thickness cap for HBM cubes, which necessitates thinner dies and narrower gaps for increased DRAM layers, posing manufacturing challenges for current technologies.