Chinese IMECAS develops DUV-based stacked-nanosheet GAA transistor process

Experimental Process for GAA Transistors

The Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has created an experimental process flow for building stacked-nanosheet gate-all-around (GAA) transistors. This process utilizes immersion DUV lithography, rather than EUV scanners, and has successfully demonstrated functional devices. The goal is to enable Chinese chipmakers to develop 3nm-class and smaller process technologies despite restrictions on accessing leading-edge EUV tools.

Technical Achievement and Limitations

IMECAS reported completing 'early process integration' for these DUV-fabricated stacked nanosheet-channel GAA transistors. The experimental devices achieved Ion/Ioff ratios of 9.7×10⁵ and 7.6×10⁵, both exceeding the 5×10⁵ threshold, indicating effective gate control. However, IMECAS has not disclosed critical geometrical parameters such as gate pitch, metal pitch, nanosheet dimensions, or transistor density. This lack of detail prevents direct comparison to commercial 3nm-class transistors from manufacturers like Intel, Samsung Foundry, or TSMC. The current achievement validates a DUV-based stacked-nanosheet GAA process flow, but it is not a complete 3nm manufacturing process.

Significance for Chinese Semiconductor Development

This development is important as it shows China's ability to pursue its own path in semiconductor evolution without relying on advanced Western tools. The research focuses on fabricating GAA devices, intended for future 3nm-class and more advanced technologies, using DUV lithography. This approach is novel for advanced nodes, as volume production typically relies on EUV for such small geometries.