Intel's EMIB and Foveros Advanced Packaging Roadmaps Evolve for Future CPUs and AI Accelerators

Evolution of Advanced Packaging

Intel's high-end client and data center CPUs rely on its Embedded Multi-die Interconnect Bridge (EMIB) and Foveros technologies. These advanced packaging methods have been central to CPU and GPU designs since Intel's multi-chiplet roadmap was outlined in 2020.

The company adopted a multi-chiplet strategy to deliver performance and feature enhancements cost-efficiently and predictably, especially after challenges with its 10nm process technology. Most recent Intel client and data center CPUs utilize multiple chiplets with EMIB and Foveros.

Integrated Packaging Approach

Intel's advanced packaging roadmap shows EMIB and Foveros becoming more sophisticated to meet demands, while also simplifying for cost-sensitive products. The two technologies are increasingly complementary, acting as key building blocks for future products.

The ultimate goal is to create system-in-packages (SiPs) that are the size of 12 reticles, utilizing both EMIB and Foveros Direct 3D.

EMIB's Development

EMIB has significantly evolved since its high-volume manufacturing debut in 2017. Initially a method to connect adjacent chiplets without expensive silicon interposers, it is now a sophisticated packaging technology used in data center processors.

EMIB is also set to enable massive AI accelerators, which will be 12 times the size of a reticle and incorporate dozens of silicon dies.