← All stories
● Covered by 4 sources · 4 reportsMedium impact4 neutral

TSMC and Samsung Commit to ASML's High NA EUV Chipmaking Tools

🔄 Updated 12h ago — new reporting from Ars Technica
New to BrevFeed? We gather this story from every outlet covering it into one summary — ranked by real-world impact, not just the latest headline — so you never miss what matters. What is BrevFeed? →

Key points

  • TSMC and Samsung will use ASML's High NA EUV machines.
  • High NA EUV machines print smaller, more intricate circuit patterns.
  • Samsung plans to use the machines for DRAM production from 2028.
  • The adoption is driven by demand for advanced chips for AI.
  • TSMC will deploy ASML's High NA EUV tech by 2030.
  • Samsung and TSMC will adopt larger 12-inch photomasks.
  • 12-inch photomasks are expected in advanced node production by 2033.
  • Intel has deployed ASML's High NA EUV technology on its 18A process.
  • Intel used ASML's High NA EUV for Core Ultra Series 3 (Panther Lake) processors.
  • Intel built over one million wafers using the new process.
  • TSMC will use High-NA EUV for high-volume manufacturing.
  • TSMC will use conventional 6x6-inch photomasks initially.
  • TSMC will build a pilot line for 6x12-inch photomasks in 2031.
  • The technology change could increase chip production by 40%.
  • ASML's high NA EUV machines cost up to $400 million each.

Chipmakers Adopt Advanced Lithography

TSMC and Samsung, major global chip manufacturers, have committed to integrating ASML's High NA extreme ultraviolet (EUV) lithography machines into their production processes. These machines are crucial for printing circuit patterns onto silicon wafers and can create smaller, more intricate designs. Each High NA machine costs approximately $400 million.

Samsung's DRAM Production Plans

Samsung, a leading memory chipmaker, announced its intention to utilize ASML's High NA EUV machines for producing DRAM, a key type of memory, starting in 2028. The company stated that adopting this technology by 2030 will extend the DRAM scaling roadmap and enhance manufacturing efficiency.

TSMC Focuses on AI Applications

TSMC will deploy ASML's tools for advanced chip manufacturing. The company anticipates an increase in the use of High NA machines, primarily due to the complex transistor architectures required for artificial intelligence (AI) applications. This aligns with the growing industry demand for more powerful chips to support AI development.

Industry Initiative for Photomask Technology

Both TSMC and Samsung will also participate with ASML in an industry initiative aimed at advancing next-generation 12-inch photomask technology. This represents an upgrade from the current 6-inch format. Photomasks serve as stencils for printing patterns on wafers, and a larger format is expected to improve productivity and reduce chipmaking costs.

Market and Capacity Outlook

Intel is already a customer for ASML's High NA machines, using the technology for advanced chip manufacturing. While ASML has not provided recent sales forecasts for these machines, it plans to increase its total EUV capacity by about 30% by 2027. Analysts view these commitments from TSMC and Samsung as providing greater clarity on adoption, which is seen as positive for ASML's future growth.

Updates

🕒 2026-09-08 · new reporting from Ars Technica
  • The technology change could increase chip production by 40%.
  • ASML's high NA EUV machines cost up to $400 million each.
🕒 2026-09-08 · new reporting from Tom's Hardware
  • TSMC will use High-NA EUV for high-volume manufacturing.
  • TSMC will use conventional 6x6-inch photomasks initially.
  • TSMC will build a pilot line for 6x12-inch photomasks in 2031.
🕒 2026-09-08 · new reporting from Engadget
  • TSMC will deploy ASML's High NA EUV tech by 2030.
  • Samsung and TSMC will adopt larger 12-inch photomasks.
  • 12-inch photomasks are expected in advanced node production by 2033.
  • Intel has deployed ASML's High NA EUV technology on its 18A process.
  • Intel used ASML's High NA EUV for Core Ultra Series 3 (Panther Lake) processors.
  • Intel built over one million wafers using the new process.

✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →

The daily brief

One email each morning: the day's tech stories, clustered across outlets and summarized. No account needed.

One email a day. Unsubscribe in one click, any time.

Today's brief

Spend a few minutes, get the whole day. Every topic's top stories in one hands-free rundown — listen, watch, or read the transcript.

~8 min · 6 stories · Sep 08

▶ Play today's brief Listen on Spotify

New every morning, and the back catalogue is archived by date.

How outlets covered it

Samsung Electronics and TSMC will adopt ASML's high NA EUV photolithography machines and have agreed to a technology change that could increase chip production by 40%. This adoption signifies a broader industry embrace of advanced EUV technology for manufacturing next-generation chips.

TSMC announced plans to begin using High-NA EUV lithography for high-volume manufacturing in 2030, transitioning from current Low-NA EUV systems. This adoption is driven by the increasing complexity of transistor architectures, such as GAA transistors and CFETs, which require more advanced patterning capabilities.

Samsung and TSMC will adopt ASML's High NA extreme ultraviolet (EUV) lithography machines and larger 12-inch photomasks, following Intel's earlier deployment. This move aims to increase production capacity, boost manufacturing yields, and lower chipmaking costs for high-end chips and RAM, potentially addressing current chip shortages.

TSMC and Samsung, the world's largest chipmakers, have committed to using ASML's High NA extreme ultraviolet (EUV) lithography machines for advanced chip production, driven by increasing demand for AI applications. This adoption signifies a move towards more intricate chip designs and improved manufacturing efficiency, with Samsung planning to use the technology for DRAM production from 2028.