For years, AI hardware performance was primarily determined by GPU metrics like FLOPS, memory, and clock speed. However, hyperscalers now face challenges in achieving higher performance within existing facility footprints. The focus has shifted to the interconnect fabric between chips, which is becoming critical for continued AI hardware advancement.
Nick Harris, CEO of Lightmatter, states that Moore's Law, which historically guided silicon density improvements, is no longer applicable for AI hardware. The physical limits of single chip size mean that performance gains now depend on effectively networking dozens or hundreds of chips together. This makes networking the future of computing for AI systems, as performance is bottlenecked by latency and bandwidth.
AI infrastructure scaling involves 'scale-up' for ultra-low-latency interconnects within a single server or rack, and 'scale-out' for combining these machines into clusters. A third factor, 'scale-across,' links entire data centers. Hyperscalers are integrating between 72 and 144 GPUs into a single scale-up rack, pushing the limits of current interconnect technologies.
Copper cabling, previously sufficient for rack-level interconnects, has reached its physical and supply limitations, particularly regarding cable length. Optical interconnects are emerging as a solution, moving from traditional rack-to-rack cabling to closer integration with the accelerator package itself. This includes advancements from pluggable transceivers to near-package and co-packaged optics (CPO).
The increasing importance of optical interconnects is highlighted by recent industry moves, such as Elon Musk's acquisition of Mesh Optical as part of TeraFab and SpaceX's AI initiatives. This indicates a growing recognition of photonic interconnects as a key technology for future AI hardware development and scaling.
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The AI industry is increasingly adopting optical interconnects to overcome the physical limitations of copper cabling and traditional GPU scaling. This shift is driven by the need for higher bandwidth and lower latency in large-scale AI systems, as Moore's Law for silicon density is no longer sufficient for performance gains.