Tesla has disclosed its updated AI accelerator roadmap, outlining the future direction of its chip development. The company anticipates its 6th Generation inference accelerator will provide an 80-fold increase in compute performance compared to the existing 4th Generation chip. This indicates a substantial leap in processing capabilities for inference tasks.
A key change in the roadmap involves the Dojo D3 training accelerator. This next-generation chip will move away from an SRAM-centric architecture and adopt a multi-chiplet design incorporating stacked High Bandwidth Memory (HBM). This represents a significant departure from the original Dojo D1's system-on-wafer architecture, which used distributed on-chip SRAM and interconnected 25 D1 processors.
The shift to HBM suggests Tesla's intention to increase memory capacity, as modern AI models require large amounts of memory for parameters, activations, and intermediate data. While HBM simplifies memory scaling, it introduces different considerations regarding latency, bandwidth, packaging, and power consumption. It is not yet clear if wafer-scale integration has been entirely abandoned.
Tesla is also rebranding its AI accelerators, adopting the term "super intelligence" instead of "artificial intelligence." Consequently, the accelerators will now carry "SI" monikers. This change extends to other ventures, with SpaceXAI also being renamed SpaceXSI.
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Tesla has released its updated AI accelerator roadmap, detailing significant changes to its chip development. The company's 6th Generation inference accelerator is projected to deliver 80 times more compute performance than the current 4th Generation chip, and the D3 training accelerator will transition to a multi-chiplet design with stacked HBM, moving away from its previous SRAM-centric architecture. Tesla is also rebranding its AI accelerators with "SI" monikers, standing for "super intelligence."