XCENA and Samsung Unveil MX1 CXL Device with Integrated RISC-V Compute and SSD Support

Introducing the MX1 Memory Xcelerator

XCENA, in partnership with Samsung, has launched the MX1, a new CXL memory expansion device. The MX1 is designed to meet the increasing memory requirements of machine learning models by offering both substantial memory capacity and integrated compute capabilities.

Memory Expansion and Storage Features

The MX1 connects to a host system via a PCIe 6/CXL 3.2 x8 interface, providing 128 GB/s of bandwidth. It can host up to 2 TB of DDR5 memory. Additionally, the device includes eight downstream PCIe 6 lanes for connecting SSDs, allowing SSD storage to be exposed as memory with the MX1's DRAM acting as a cache.

Integrated RISC-V Compute

A key feature of the MX1 is its onboard compute, which consists of 3072 RISC-V cores. These cores are organized into clusters of 32, sharing L2 caches and a data TLB. Twenty-four such clusters form subsystems, which are the smallest units for job allocation, enabling the MX1 to run 24 independent jobs concurrently. Two Arm Cortex A53 cores manage control functions.

The MX1 chip is fabricated using Samsung’s 4nm process and has a power consumption of 40 W for the chip itself, with the entire board consuming 90W when including four DIMMs. The design prioritizes data-parallel workloads, similar to Intel's Xeon Phi, by using many small, power-efficient cores.

Core Architecture and Cache Hierarchy

Each RISC-V core operates at 1.1 GHz and uses in-order execution. The MX1's cache hierarchy is designed to minimize address translation overhead. Each core has a 4 KB virtually addressed L1 data cache. L2 data caches, 128 KB in size, are shared across clusters and are virtually indexed and physically tagged (VIPT).