● Covered by 1 source · 1 reportMedium impact
JEDEC introduces SPHBM4 standard to reduce costs of high-bandwidth memory
Key points
- New SPHBM4 standard combines HBM4 DRAM with a 512-bit interface
- Eliminates need for expensive interposers and uses organic substrates
- Supports data rates between 22.4 GT/s to 46.0 GT/s
Introduction of SPHBM4 Standard
JEDEC has introduced the Standard Package High Bandwidth Memory (SPHBM4) standard to help decrease the costs associated with high-bandwidth memory (HBM) vital for AI processors.
This new specification is detailed in JESD330-4 and offers a 512-bit interface, differing from the wider interfaces used in earlier HBM generations.
Cost-Effective Implementation
The SPHBM4 standard allows for the use of standard organic substrates instead of relying on advanced packaging techniques like TSMC’s CoWoS.
By not using expensive interposers, manufacturers can reduce overall costs for memory solutions while still utilizing HBM4 DRAM stacks.
Performance Characteristics
Although the SPHBM4 has a narrower 512-bit interface, it compensates by supporting data rates of 22.4 GT/s to 46.0 GT/s.
This approach groups the internal HBM4 channels into Quad Channels, allowing for effective data transfer without requiring additional pins.
Limitations
Despite its advantages, the SPHBM4 standard does not enhance the speed of the DRAM array itself; it maintains the existing architecture and timings of HBM4.
This specification primarily addresses cost issues but does not contribute to alleviating the current DRAM supply challenges.
✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →
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Reporting from
JEDEC has released the SPHBM4 standard, which enables cheaper high-bandwidth memory (HBM) by allowing the use of organic substrates and eliminating the need for costly interposers. It utilizes a narrower 512-bit interface while maintaining high data transfer rates, potentially lowering memory costs in AI processors without addressing the DRAM shortage.