JEDEC has released the SPHBM4 standard, which enables cheaper high-bandwidth memory (HBM) by allowing the use of organic substrates and eliminating the need for costly interposers. It utilizes a narrower 512-bit interface while maintaining high data transfer rates, potentially lowering memory costs in AI processors without addressing the DRAM shortage.
JEDEC has introduced the Standard Package High Bandwidth Memory (SPHBM4) standard to help decrease the costs associated with high-bandwidth memory (HBM) vital for AI processors.
This new specification is detailed in JESD330-4 and offers a 512-bit interface, differing from the wider interfaces used in earlier HBM generations.
The SPHBM4 standard allows for the use of standard organic substrates instead of relying on advanced packaging techniques like TSMC’s CoWoS.
By not using expensive interposers, manufacturers can reduce overall costs for memory solutions while still utilizing HBM4 DRAM stacks.
Although the SPHBM4 has a narrower 512-bit interface, it compensates by supporting data rates of 22.4 GT/s to 46.0 GT/s.
This approach groups the internal HBM4 channels into Quad Channels, allowing for effective data transfer without requiring additional pins.
Despite its advantages, the SPHBM4 standard does not enhance the speed of the DRAM array itself; it maintains the existing architecture and timings of HBM4.
This specification primarily addresses cost issues but does not contribute to alleviating the current DRAM supply challenges.
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JEDEC has released the SPHBM4 standard, which enables cheaper high-bandwidth memory (HBM) by allowing the use of organic substrates and eliminating the need for costly interposers. It utilizes a narrower 512-bit interface while maintaining high data transfer rates, potentially lowering memory costs in AI processors without addressing the DRAM shortage.