Google opts for Intel's EMIB-T packaging for next-gen TPUs over TSMC technology

Google's Transition to EMIB-T Packaging

Google plans to integrate Intel's EMIB-T packaging in its Ninth-Generation TPUs, codenamed Humufish, as reported by SemiAnalysis. This switch from TSMC's previously favored CoWoS technology underscores the evolving landscape of advanced packaging solutions in the industry.

Background on Google and TSMC's CoWoS

For many years, Google utilized TSMC's chip-on-wafer-on-substrate (CoWoS) technology for its TPUs, starting with the Third-Generation up to the Eighth-Generation TPUs. CoWoS has been the predominant choice for high-performance computing and AI processors, due to its effective capacity and performance.

Understanding the EMIB-T Technology

Unlike CoWoS, Intel's EMIB technology eliminates the use of interposers, relying instead on embedded silicon bridges to create a high-density die-to-die connection within an organic substrate. The EMIB-T variant further enhances this technology by adding through-silicon vias (TSVs) for improved power distribution.

Implications for Advanced Packaging

Google's decision to transition to EMIB-T could provide insights into the competitive packaging landscape between Intel and TSMC. The shift indicates a search for alternatives in advanced packaging technology, possibly driven by supply limitations or performance considerations associated with TSMC's offerings.

Conclusion and Industry Impact

This move by Google may influence other chip designers and hyperscalers exploring packaging alternatives. The growing adoption of EMIB-T could signal a shift towards diversified sources for advanced packaging solutions, impacting the dynamics of the AI and HPC markets.