CXMT to launch first 4F² DRAM, a server DDR5 RDIMM, by year-end

CXMT's First 4F² DRAM Product

CXMT President Cao Kanyu announced that the company will launch its first 4F² DRAM product, a server DDR5 RDIMM, by the end of the current year. This new memory module will utilize a denser cell layout, which has not yet been commercialized in the industry. The technology employs vertical transistors to achieve a cell footprint reduction of approximately one-third compared to current designs.

Technical Details of 4F² Technology

The 4F² cell design measures 2F by 2F, occupying about two-thirds the area of existing 6F² cells at the same feature size. CXMT's specific implementation, called the Vertical Surrounded Gate (VSG) transistor, features a vertical channel surrounded by a gate. This configuration allows for stronger gate control and reduced leakage, primarily contributing to the smaller cell size. CXMT holds over 300 patent families related to 4F² technology and has presented research on it since 2021, including an 8Gb full-array research example demonstrated at IEDM 2023.

Industry Shift Towards 4F²

The memory industry is generally moving towards 4F² designs, often incorporating 3D solutions that separate DRAM and CMOS processes. These are then combined using wafer-level hybrid bonding, which allows independent optimization of logic and cell density. CXMT has also been involved in hybrid-bonding research since 2019, with published patents in this area.

CXMT's Recent Growth and Developments

This announcement follows other recent developments from CXMT, China's primary DRAM manufacturer. The company's fifth-generation G5 DRAM technology platform entered mass production on September 20. TrendForce reported CXMT's share of global DRAM revenue increased to 9.5% in the second quarter, up from 7.6% in the first quarter, placing it fourth globally. In November, CXMT showcased DDR5-8000 and LPDDR5X-10667, indicating its growing presence in the memory market.

Competitor Activities in 4F² DRAM

Other major players are also developing 4F² DRAM. Samsung presented a 16Gb, 10nm-class 4F² DRAM design in February, also utilizing vertical-channel transistors (VCT) and wafer-to-wafer hybrid copper bonding. Samsung claims this bonding method increases dies per wafer by over 20%. Reports in April indicated Samsung had a working 4F² VCT die on its sub-10nm “10a” process, with mass production initially targeted for 2028, though subsequent reports have introduced uncertainty regarding this timeline.