Intel Details Xeon 7 'Diamond Rapids' CPUs with up to 256 P-cores and 1.28 GB LLC

Next-Gen Xeon Details Revealed

Intel has provided further information regarding its upcoming Xeon 7 'Diamond Rapids' CPUs, following earlier teasers. These processors are designed for data centers and are slated for a 2027 release. Key specifications include a maximum of 256 P-cores and 1.28 GB of last-level cache.

Architectural and Process Advancements

The Diamond Rapids range incorporates several anticipated advancements from Intel's roadmap. These include the enhanced 18A-P process technology, the adoption of UCIe interconnects, and support for AVX 10.2. Intel's new 'fan-out' fabric is also part of this generation.

While the core architecture, known as Panther Cove, was not fully detailed during the Hot Chips 2026 presentation, Intel did provide a technical overview of the chip's broader construction.

Compute Tile Structure

Intel refers to the compute tiles as Compute Building Blocks (CBBs). Each CBB consists of a core chiplet stacked on a base tile that houses the last-level cache. A single core chiplet can contain up to 16 cores, and a CBB can accommodate up to four such chiplets. These chiplets connect to the base tile via a 3D Xbar.

A complete Diamond Rapids SoC comprises four base tiles built on Intel 3-T, two fabric hub tiles built on Intel 3, and 16 core chiplets built on Intel 18A-P.

Advanced Packaging Techniques

The integration of these components relies on two advanced packaging techniques. Intel uses its Foveros Direct 3D technology to bond the compute tiles to the base tiles, a method also seen in Xeon 6+ 'Clearwater Forest' CPUs. For connecting the fabric hub tiles to the cores, Intel utilizes UCIe-S with a copper connection. Notably, this generation moves away from Intel's Embedded Multi-die Interconnect Bridge (EMIB), which has been widely used in previous products.