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Intel processes over one million High-NA EUV wafers, plans larger 6x12 photomasks
Key points
- Intel processed over one million 300-mm wafers with High-NA EUV scanners.
- This figure surpasses the rest of the industry's combined High-NA EUV wafer processing.
- Intel is developing 6x12-inch photomasks for full-field High-NA EUV exposure.
- Current High-NA EUV requires stitching for large chips, reducing throughput.
High-NA EUV Wafer Milestone
Intel announced it has processed more than one million 300-mm wafers using its High-NA EUV scanners. This milestone was achieved less than two and a half years after the first tool was assembled. The one million wafer figure includes wafers processed during tool installation, certification, R&D, and production.
Industry Leadership in High-NA EUV
Intel's achievement signifies a significant lead in High-NA EUV utilization. Earlier this year, Intel certified High-NA EUV scanners for its 18A process technology, which are now used for some Panther Lake processors. Intel currently operates two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. This milestone indicates a substantial increase in cumulative High-NA utilization, with Intel processing more wafers using High-NA tools than the rest of the industry combined, according to ASML's April announcement regarding total wafers processed by all shipped High-NA EUV scanners.
Addressing Stitching Limitations
Currently, High-NA EUV uses anamorphic 4X/8X magnification, meaning standard 6-inch photomasks can only expose approximately 26x16.5 mm on the wafer. Larger dies require 'stitching,' where two half-fields are exposed. This process reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B and necessitates specific chip design considerations, limiting floor planning freedom.
Future Photomask Development
To overcome the limitations of stitching, Intel is working on larger 6x12-inch photomasks. These larger masks would enable High-NA EUV scanners to expose full 26x33 mm fields without the need for stitching. This development aims to improve throughput and provide greater flexibility in chip design for future processes.
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Reporting from
Intel announced it has processed over one million 300-mm wafers using High-NA EUV scanners, exceeding the combined total of the rest of the industry. The company is also developing larger 6x12-inch photomasks to eliminate stitching for full-field exposures, which currently reduces throughput and design flexibility.