● Covered by 1 source · 1 reportMedium impact1 neutral
Synopsys Validates PCIe 6.0 PHY in 3D Stack at 64 GT/s
Key points
- Synopsys validated a 5nm PCIe 6.0 PHY in a 3D face-to-face stacked package.
- The PHY achieved 64 GT/s per lane and 128 GB/s across an eight-lane link.
- Validation involved modifying an existing 2D test chip with TSVs and 3D design kits.
- Integrating PCIe PHYs in 3D stacks presents challenges due to signal routing and electromigration.
3D PCIe 6.0 Validation Achieved
Synopsys has released silicon results for what it claims is the first 3D PCIe 6.0 test chip. This 5nm PHY, integrated into a face-to-face stacked package, operates at 64 GT/s per lane and achieves up to 128 GB/s over an eight-lane link using PAM4 signaling. The receiver eyes met the standard's bit error rate requirements.
Development Process
The company developed this 3D solution by adapting an existing 2D PCIe 6.0 test chip. This involved adding through-silicon vias (TSVs) and re-engineering the circuit design and signoff processes to align with 3D process design kits.
Challenges of 3D Integration
Integrating PCIe PHYs into 3D face-to-face stacked packages presents significant challenges. In traditional monolithic or 2.5D designs, PHYs are positioned at the die's perimeter for short traces to package I/O. However, face-to-face hybrid bonding flips the bottom die, orienting PHYs away from the substrate. Signals must then travel through TSVs, which require buffers and impact routing. Electromigration and layout rules also change substantially in 3D environments, and the placement of customer logic over the PHY's path adds complexity.
Signaling and Future Implications
The use of PAM4 signaling, which packs two bits per symbol, leaves less margin for error compared to the NRZ signaling used in PCIe 5.0 and earlier. This validation by Synopsys is significant as PCIe generations are accelerating, with new specifications releasing approximately every two years. Addressing the challenges of high-speed I/O integration in 3D stacks is critical for the continued scaling of computing performance.
✨ This summary was generated by AI from the outlets' reporting listed below. It is not independently verified and may contain errors — check the original sources. How BrevFeed works →
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Reporting from
Synopsys has published silicon results for a 3D PCIe 6.0 test chip, demonstrating a 5nm PHY operating at 64 GT/s per lane in a face-to-face stacked package. This validation addresses the challenges of integrating high-speed I/O like PCIe into 3D chip stacks, which is crucial for future high-performance computing architectures.